Metal oxide semiconductor field effect transistors (MOSFET) have seen increased use in recent years in very large scale integrated circuits (VLSI). MOSFET integrated circuits provide high component density and simple process technology as compared with bipolar integrated circuits. High density MOSFET technology is particularly applicable for memory circuits.
As integrated circuit density increases, the number of transistors connected to a single extended signal line can increase substantially. For example, in a memory circuit the number of memory cells connected to a word line can increase by as much as a factor of four in progressing from a 16K device to a 64K device. Each interconnecting line, or "run" as it is more typically called, is normally driven by a peripheral circuit such as a decoder in a memory.
In certain applications it is necessary to simultaneously apply a signal to a plurality of transistor gates connected along a single run. The signal transmitted along a run is subject to time delay and distortion due to the series resistance of the run coupled with the effective shunt capacitance of the combination of all of the interconnected transistor gates that are attached to the run but are not conducting. However, when it becomes necessary for a transistor near a signal generating circuit to receive a signal simultaneously with a transistor far from the signal generating circuit, the delay along the run can degrade the performance. The series resistance of the run is a function of the length to width ratio of the run and the type of material utilized. As geometries become smaller, and run lengths stay essentially the same, the length to width ratio increases, thus increasing the series resistance at the run. Shunt capacitance of a run is primarily due to the capacitance of the conductive surface area of the gate electrode separated by the source and drain regions by the insulating gate oxide. Although the shunt capacitance decreases proportionately with the size of the gate electrode, the shunt capacitance increases as the gate oxide thickness is reduced. As the density of MOSFET circuits has increased, the gate oxide thickness has decreased from approximately 800 to 1,000 angstroms with 16K memories to a thickness of approximately 300 to 500 angstroms with current 64K memories. It can therefore be seen that the resistance and capacitance of runs is tending to increase with higher densities.
In applications where it is necessary to drive one transistor on the end of a long run of parallel transitors, the equivalent circuit of the run appears as a distributed capacitor. This distributed capacitor is made up of a plurality of series R/shunt C L-sections. The series R is a function of the length of the run between adjacent transistors while the shunt C is the capacitance due to the conductive surface area of the gate electrodes that overlies the source and drain areas of each individual transistor. When considering a high density circuit such as a 64K static random access memory (RAM), each row can have 256 transistors in parallel with an individual run. This results in 255 idle transistors loading the run when the furthermost transistor is driven. Each of the series R/shunt C L-sections has an associated R-C time constant, which, when added together, results in a delay that places a limitation on the maximum switching speed at which the circuit may operate.
Heretofore the conventional process for fabricating runs comprises depositing and etching a plurality of polycrystalline silicon (polysilicon) lines. These polysilicon lines are then doped with impurities to increase their conductivity. The typical values for series resistance of doped polysilicon lines is 25 to 50 ohms per square. A square is defined as an area of conductor of uniform thickness with equal side dimensions wherein the series resistance for a 1".times.1" square is the same as for a 0.001".times.0.001" square.
The conventional process for fabricating a MOSFET transistor includes the steps of depositing, patterning and etching a layer of polysilicon to define a conductive gate electrode over the channel region of a transistor. Impurities are then introduced into the gate and substrate on either side of the gate electrode to define the source and drain regions of the transistor. Ion implantation has been used to substantially improve the definition of the boundaries for the source and drain regions are compared to vapor deposition techniques. However, there remains some lateral diffusion of impurities under the gate electrode causing the conductor portions of the source and drain regions to "creep" under the gate electrode. A virtual capacitor is formed in this process by the overlap of the gate electrode and either the source or drain region separated by the gate oxide layer which provides the dielectric of the capacitor. The extent of lateral diffusion of impurities under the gate electrode remains essentially constant regardless of circuit density due to the nature of ion implantation.
In view of the time delay problems caused by the increasing resistance and capacitance of runs in integrated circuits resulting from smaller geometries and higher densities, there exists a need for a method for fabricating such runs to have less resistance and capacitance.